Data processing systems which use virtual addressing in multiple virtual address spaces are well known and include systems such as, for instance, the IBM System/390 using MVS controlled programming. The organization and hardware/architectural aspects of the IBM System/390 are described in "IBM System/390 Principles of Operation," Form No. SA22-7201-00. The MVS system, as well as many other data processing systems, includes, for example, a central processing unit (CPU) and a main storage. The CPU contains the sequencing and processing facilities for instruction execution, interruption action, timing functions, initial program loading and other machine related functions. The main storage is directly addressable and provides for high-speed processing of data by the CPU. The main storage may be either physically integrated with the CPU or constructed in stand-alone units.
In general, address spaces reside in main storage wherein an address space is a consecutive sequence of integer numbers (or virtual addresses), together with the specific transformation parameters which allow each number to be associated with a byte location in storage. The sequence starts at zero and proceeds left to right.
When a virtual address is used by a CPU to access main storage, it is first converted, by means of dynamic address translation (DAT), to a real address, and then, by means of prefixing, to an absolute address. DAT uses two levels of tables (segment tables and page tables) as transformation parameters. The designation (origin and length) of a segment table is found for use by DAT in a control register or as specified by an access register.
DAT uses, at different times, the segment-table designations in different control registers or specified by the access registers. The choice is determined by the translation mode specified in the current program-status word (PSW). Four translation modes are available: primary-space mode, secondary-space mode, access-register mode (AR-mode), and home-space mode. Different address spaces are addressable depending on the translation mode.
At any instant when the CPU is in the primary-space mode or secondary-space mode, the CPU can translate virtual addresses belonging to two address spaces--the primary address space and the secondary address space. At any instant when the CPU is in the access-register mode, it can translate virtual addresses of up to 16 address spaces--the primary address space and up to 15 AR-specified address spaces. At any instant when the CPU is in the home-space mode, it can translate virtual addresses of the home address space.
The primary address space is identified as such because it consists of primary virtual addresses, which are translated by means of the primary segment-table designation. Similarly, the secondary address space consists of secondary virtual,addresses translated by means of the secondary segment-table designation, the AR-specified address spaces consist of AR-specified virtual addresses translated by means of AR-specified segment-table designations, and the home address space consists of home virtual addresses translated by means of the home segment-table designation. The primary and secondary segment-table designations are in control registers 1 and 7, respectively. The AR-specified segment-table designations are in control registers 1 and 7 and in table entries called ASN-second-table entries. The home segment-table designation is in control register 13.
Access register mode is described in U.S. Pat. No. 5,023,773 entitled "Authorization for Selective Program Access to Data and Multiple Address Spaces" issued on Jun. 11, 1991 and assigned to International Business Machines Corp. Described within the patent is a program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. The multiple address space facility provides 16 32-bit access registers and when operating in access register mode, one of the access registers is used to specify the address space to which the logical address is relative by specifying a segment-table designation used by DAT to translate the logical address for the address space.
A program can cause different address spaces to be addressable by using, for example, the semiprivileged SET ADDRESS SPACE CONTROL instruction to change the translation mode to the primary-space mode, or home-space mode. However, SET ADDRESS SPACE CONTROL can set the home-space mode only in the supervisor state. The program can cause still other address spaces to be addressable by using other semiprivileged instructions to change the segment-table designations in control registers 1 and 7 and by using unprivileged instructions to change the contents of the access registers. Only the privileged LOAD CONTROL instruction is available for changing the home segment-table designation in control register 13.
The home address space facility is described in U.S. Pat. No. 4,943,913, entitled "Operating System Accessing Control Blocks By Using Home Address Space Segment Table To Control Instruction And Operand Fetch and Store Operations" issued on Jul. 24, 1990 and assigned to International Business Machines Corp. In particular, a method for providing a way for the operating system to access instructions and data in a multiple address space environment is described. The method includes the steps of dispatching the highest priority address space with a dispatchable unit of work as a home address space which contains control blocks for defining the dispatchable unit of work, loading a pointer to a segment table for the home address space in one of the control registers to provide for virtual address translation in the home address space, setting address space control bits in a field of the program status word in the CPU thereby identifying a home mode and causing the home address space segment table to be the one to be used by DAT to translate virtual addresses and data in the home address space, and accessing the control blocks by the operating system using the home address space segment table to predictably control instruction and operand fetch and store operations from and to the home address space for the dispatchable unit of work in the home address space.
An address space may be assigned an address space number (ASN) by the control program. The ASN designates, within a two-level table structure in main storage, an ASN-second-table entry containing information about the address space. If the ASN-second-table entry is marked as valid, it contains the segment-table designation that defines the address space.
Under certain circumstances, the semiprivileged instructions which place a new segment-table designation in control register 1 or 7 fetch this segment-table designation from an ASN-second-table entry. Some of these instructions use an ASN-translation mechanism which, given an ASN, can locate the designated ASN-second-table entry.
The ASNs for the primary and secondary address spaces are assigned positions in control registers. The ASN for the primary address space, called the primary ASN, is assigned bits 16-31 of control register 4, and that for the secondary address space, called secondary ASN, is assigned bits 16-31 of control register 3.
Address spaces may be used to provide degrees of isolation between users. There can be a completely different address space for each user, thus providing complete isolation, or there can be a shared area which is provided by mapping a portion of each address space to a single common storage area. In addition, one program in one address space can access data or call a program in another address space (referred to as cross-memory mode), as described in U.S. Pat. No. 4,366,537 issued on Dec. 28, 1982 and assigned to International Business Machines Corp.
In U.S. Pat. No. 4,366,537 entitled "Authorization Mechanism for Transfer of Program Control or Data Between Different Address Spaces Having Different Storage Protect Keys", the use of storage protect key masks and the provision of basic authority control with dual address space memory references, program subsystem linkages and address space number translation to main memory addresses with authorization control is described. The ability to move information from a primary address space to a secondary address space includes a secondary-segment table, which is defined by a secondary-segment table origin and secondary-segment table length. An instruction, MOVE TO SECONDARY, is used in moving data between the primary address space and the secondary address space.
The order in which instructions are executed in an address space is controlled by a program status word (PSW). The PSW further indicates the status of the system in relation to the program currently being executed. Each processor has only one current PSW.
The current PSW is the hardware information in the CPU that indicates the next instruction to be executed. It also indicates whether the CPU is enabled or disabled for I/O interruptions, external interruptions, machine check interruptions and certain program interruptions. When the CPU is enabled, these interruptions can occur. When the CPU is disabled, these interruptions are ignored and remain pending. (A pending interruption is processed when the unit of work that is executing in the disable state enables.)
A task control block (TCB) is a dispatchable unit of work represented by control blocks which represent tasks executing within an address space. The tasks may include, for instance, user programs and system programs executed to support the user programs. TCBs are created in response to an ATTACH macro instruction. By issuing ATTACH, a user or system routine causes the supervisor to begin the execution of the program specified on the ATTACH macro as a subtask of the caller's task. As a subtask, the specified program can compete for CPU time and may use certain resources already allocated to the caller's task.
The TCB is used to maintain CPU status of a process (program) that has been preempted and is not currently executing on the CPU. Typical CPU status would include the general purpose registers (GPRs), the PSW, the primary ASN (PASN) and the secondary ASN (SASN) discussed below.
The PASN can be loaded by means of a PROGRAM CALL with space switching, a PROGRAM TRANSFER with space switching, PROGRAM RETURN or a LOAD ADDRESS SPACE PARAMETERS instruction. When the PASN is loaded by means of the above instructions, the corresponding segment table designator (STD) is placed in the primary segment table designator (PSTD), bits 0-31 of control register 1. The PASN can also be loaded by means of LOAD CONTROL, in which case no translation occurs to convert the PASN to STD.
When the SASN is loaded by means of the above instructions, the corresponding STD is placed in the secondary segment table designation (SSTD), bits 0-31 of control register 7. SASN can be loaded by means of LOAD CONTROL, in which case no translation occurs to convert the SASN to STD.
While the prior art describes methods for allowing programs running in one address space to PROGRAM CALL to another address space (cross-memory mode), the prior art does not allow MVS services, such as SUPERVISOR CALL instructions, to be executed in cross-memory mode. In addition, there is no facility for allowing an address space to PROGRAM CALL to the home address space while executing under the dispatchable unit of the home space. Further, the prior art, in particular the home address space facility, is restricted to priviledged programs that must reside in common storage and again most MVS services are unavailable in this mode. In addition, the prior art does not allow for a PROGRAM CALL to the home space when all the callers associated with the PROGRAM CALL are unknown.
Therefore, a need exists for providing a PROGRAM CALL to a dispatchable unit's base space in which the restrictions associated with the prior art and cross-memory mode are eliminated. Further, a need exists for a fast mechanism for leaving the cross memory environment thereby enabling access to the MVS services, (such as ENQ, OPEN, SVC, etc.). A further need exists for allowing unauthorized callers access to the base address space. A further need exists for a mechanism which readily provides access to both code and data in the base address space. In addition, a need exists for a mechanism which enables cross memory servers to run user exits in the home or base address space and exploit the ESA linkage stack via Stacking PC (e.g., to restore user authority) without requiring the cross memory server to have prior knowledge of all its callers.